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1
Проектирование цифровых устройств на основе ПЛИС фирмы XILINX в САПР WebPACK ISE
Горячая линия Телеком
Зотов В.Ю.
bc_2
bc_1
input
internal
inout
output3
xon
std_ulogic
msgon
controlr
pull0
symattr
vitaldelaytype
downto
warning
sch
last_event
msgseverity
void
std_logic
bit_vector
boolean
vitaldelaytype01
1nosynth
instancepath
sympin
static
to_x01
signal
violation
vhdl
headermsg
attribute
verilog
checkenabled
testdelay
testsignal
testsignalname
wsynop
wsynth
vitaltimingdatainit
vitaltimingdatatype
valuetype
refdelay
refsignal
refsignalname
reftransition
timingdata
vitalwiredelay
library
Year:
2003
Language:
russian
File:
ZIP, 52.56 MB
Your tags:
0
/
0
russian, 2003
2
VHDL Modelling Guidelines
Creasey R.
,
Coirault R.
vhdl
timing
signal
package
simulation
signals
issue
input
agency
values
integer
library
clk
output
std_ulogic
models
timearray
reset
verification
component
declaration
parameters
architecture
std_ulogic_vector
function
packages
reset_n
declarations
valid
bit_vector
range
port
serial
board
recommended
defined
error
functionality
ieee.std_logic_1164
simcondition
specified
delay
elsif
errors
modelled
report
severity
subprograms
testbench
constants
Year:
1994
Language:
english
File:
PDF, 386 KB
Your tags:
0
/
0
english, 1994
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